Powered by Altera Stratix IV GX/GT FPGA, this platform features x8 end-point PCI Express Gen 2 / 3 , USB 3.0 (Host & Device), SFP+ , Gigabit Ethernet,  DDR-3 (SO-DIMM), DDR-2 (component), data-rate-adjustable Serial Transceivers (with super clock),  IO expansion connector, SMAs (connected to 4 Serial Transceivers), and stand-alone operation.

The on-board Super Clock provides different reference clocks across eight Serial Transceivers on the high-speed connector. This enables development with any serial IO standard supported by the on-board Stratix IV GX/GT device.

This platform supports the following Stratix IV GX/GT devices in 1517 package:

Feature	EPEP4S100G2	EEP4S100G55	EP4SGX230	EP4SGX360	EP4SGX530
Package Pin Count	1517	1517	1517	1517	1517
ALMs	91,200	212,480	91,200	141,440	212,480
LEs	228,000	531,200	228,000	353,600	531,200
Total Transceiver Channels	36	36	36	36	36
10G Transceiver   Channels (600 Mbps - 11.3 Gbps with PMA + PCS)	24	24	0	0	0
8G Transceiver Channels (600 Mbps - 8.5 Gbps with PMA + PCS)	0	0	24	24	24
PMA-only CMU Channels (600 Mbps- 6.5 Gbps)	12	12	12	12	12
PCI Express hard IP Blocks	2	2	2	2	2
High-Speed LVDS SERDES (up to 1.6 Gbps)	46	46	88	88	88
SP1-4.2 Links	2	2	4	4	4
M9K Blocks (256 × 72 bits)	1,235	1,280	1,235	1,248	1,280
M144K Blocks (2048 × 72 bits)	22	64	22	48	64
Total Memory (MLAB + M9K + M144K) Kbits	17,133	27,376	17,133	22,564	27,376
Embedded Multi18 × 18	1,024	1,024	1,288	1,040	1,024
PLLs	8	12	8	8	8
User I/Os	654	781	744	744	744
Speed Grade (fastest to slowest	–1, –2, –3	–1, –2, –3	-2, -3, -4	-2, -3, -4	-2, -3, -4

FPGA board with CX4/SATA Module (Larger Image)

Back side of the board with DDR3 SODIMM (Larger Image)

FPGA board with SFP+ Module (Larger Image)

1G/10G Interface Block Diagram