Low latency 1G/10G Ethernet MAC IP Core

Overview:

The 10Gbps 32-bit Ethernet IP core solution offers a fully integrated IEEE802.3-2008 (802.3ae) compliant package for NIC (Network Interface Card) and Ethernet switching applications.  This extremely low latency solution is specifically targeted for demanding financial, high frequency trading and HPC applications.  The 10Gbps Ethernet IP core includes:

·         Lowest latency MAC; Tx = 41.6ns , Rx = 76.8ns; (32-bit user interface mode)

·         Flexible 10GBase-R PCS options with XFI interface for direct SFP+/XFP attachment

·         Technology dependent transceiver wrapper for Altera and/or Xilinx FPGAs

·         Statistics counter block (for RMON and MIB)

·         MDIO and I2C cores for external module and optical module status/control

A complete reference design using a L2 (MAC level) packet generator/checker is also included to facilitate quick integration of the Ethernet IP in a user design.  A GUI application interacts with the reference design’s hardware elements through a PCIe interface (a UART option is also available).  A basic Linux PCIe driver/API is also provided for memory mapped read/write access to the internal registers. 

MAC core is designed with 32-bit data path operating at 312.5MHz to take advantage of high performance fabrics of the 45nm and 28nm FPGAs. This implementation approach also delivers industry’s lowest latency and low area footprint. 

Depending on the target vendor and device family, PCS layer can be a soft solution using 10.3125Gbps transceiver or an integrated Hard-IP (like in Altera’s Stratix V device).  PCS implementations are based upon 64-bit data path operating at 156.25MHz. 

As the PCS and transceiver wrapper is included with the Ethernet IP solution, the line side directly connects the 10.3125Gbps FPGA transceiver to the optical module (SFP+, XFP etc). 

Ethernet IP solution implements two user (application) side interfaces.  The register access port can either be a 32-bit AXI4 interface or a 32-bit Avalon-MM interface.  IP solution provides a highly flexible 10Gbps traffic port interface options.  Depending upon the application layer, user can select an AXI-4 streaming bus or an Avalon Streaming bus to interface with the MAC block.  In either mode, the MAC interface bus width is selectable as 32-bit @ 312.5MHz or 64-bit @ 156.25MHz.

10Gbps Ethernet IP supports advanced features like per-priority pause frames (compliant with 802.3bd specifications) to enable Converged Enhanced Ethernet (CEE) applications like data center bridging that employ IEEE 802.1Qbb Priority Flow Control (PFC) to pause traffic based on the priority levels.

Main Features:

● Implements the full 802.3 specification with preamble/SFD generation, frame padding generation, CRC generation and checking on transmit and receive respectively.

● Implements 802.3bd specification with ability to generate and recognize PFC pause frames.

● Implements reconciliation sublayer functionality with start and terminate control characters alignment, error control character and fault sequence insertion and detection.

● Multiple user interface options for the MAC data path; AXI-4 streaming or Avalon Streaming; 32-bit data path 312.5MHz or 64-bit datapath 156.25MHz

● PCS layer XGMII interface implemented as 64-bit (single data rate) SDR interface at 156.25MHz for direct interface to 10GBase-R, XAUI and RXUAI cores

●Deficit Idle Count (DIC) mechanism to ensure data rates of 10Gbps at the transmit interface.

● Optional padding of frames if the size of frame is less than 64 bytes.

● Implements fully automated XON and XOFF Pause Frame (802.3 Annex 31A) generation and termination providing flow control without user application intervention. Non PFC Mode only.

● Pause frame generation additionally controllable by user application offering flexible traffic flow control.

● Support for VLAN tagged frames according to IEEE 802.1Q.

● Support any type of Ethernet Frames such as SNAP / LLC, Ethernet II/DIX or IP traffic.

● Discards frames with mismatching destination address on receive (except Broadcast and Multicast frames).

● Programmable Promiscuous mode support to omit MAC destination address checking on receive path.

● Optional multicast address filtering with 64-bit HASH Filtering table providing imperfect filtering to  reduce load on higher layers.

● CRC-32 generation and checking at high speed using Galois field multipliers and alternate polynomials.

● Optional prevention of CRC appending in frame data by MAC to allow CRC to be pre-embedded in frame data by user application.

● Optional insertion of error control character in transmitted frame data.

● Optional forwarding of the CRC field to user application interface.

● Programmable frame maximum length providing support for any standard or proprietary frame length (e.g. 9K-Bytes Jumbo Frames).

● Status signals available with each Frame on the user interface providing information such as frame length, VLAN frame type indication and error information.

● Optional padding termination on RX path for NIC applications or forwarding of unmodified data to the user interface.

● Optional internal XGMII Loop-back.

● Statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames.

● Altera Avalon or Xilinx AXI4 interface compliant user (FIFO) interface.

● Transmit and Receive FIFOs with configurable depths having a default depth of 1KB/512B (128 64-bit/32-bit words) each, according to user interface bus width.

● Implements statistics and event signals providing support for 802.3 basic and mandatory managed objects as well as IETF Management Information Database (MIB) package (RFC 2665) and Remote Network Monitoring (RMON) required in SNMP environments.

PCS Options

● Multiple 10GBase-R PCS options are supported by the 10G Ethernet solution, including;

§      Xilinx’s 10GBase-R (free of cost) core; Default option for Xilinx;  Nearly all PCS blocks are part of the Xilinx transceiver’s Hard-IP

§       10GBase-R core; Default option for Altera, except for Stratix V family

§      Altera’s soft 10GBase-R core (require licensing from Altera)

§      Altera’s integrated 10GBase-R hard-IP (Stratix V only)

●For devices without the support for the 10.3125Gbps transceivers, Ethernet IP solution can be configured to operate with vendor specific XAUI and RXAUI cores

Licensing and Maintenance

• True sign once licensing with NO yearly maintenance fees

• Basic core licensing for a single vendor (either Xilinx or Altera) compiled (synthesized) binary 

• Additional vendor license provided at only 50% cost of the base license.  This allows for cost effective multi-vendor designs with identical user and control interfaces.
   

• Other licensing options include:

o        - Vendor and device family agnostic source code (Verilog) license
-A low cost node locked license for low budget  prototyping (upgradeable to full license after paying the cost difference only)  

MAC Resource Utilization

The MAC core utilization summary of the 10G Ethernet solution is given in following tables.  The utilization numbers are best in class as compared to other available 10G Ethernet cores with comparable feature set.  Total Ethernet utilization is dependent upon PCS core and device selection.  In best case scenario, with integrated 10GBase-R hard IP (in Altera’s Stratix V series and Xilinx Virtex-6, Virtex-7, Kintex-7 series FPGAs), total resource utilization is approximately equal to MAC core utilization. 

The Ethernet solution has been fully verified on different hardware platforms for both Altera and Xilinx FPGAs and has also been verified for interoperability with other 10G capable devices.

10G MAC - Resource Usage for Xilinx Devices

10G MAC - Resource Usage for Altera Devices

MAC Performance (Latency) 

The performance of the Ethernet MAC core is represented here in terms of individual latencies of transmit and receive paths, i.e. the time between the first bit of data input and the first bit of data output.  This numbers will change with the change in programmable threshold levels used for reading the user interface FIFOs.  For the latencies given here, the thresholds for both transmit and receive User FIFOs were set to 1 and testing was done using 64 bytes of frame data.  Data path latency is also dependent upon the type of user interface FIFO used in the design.  FIFO implementation can either be a SCFIFO (Single Clock FIFO, when the MAC and application clock are same) or can be a DCFIFO (Dual Clock FIFO, when the MAC and application clock are different).  Following table lists the latencies for various user interface options. 

Deliverables 

·         Compiled synthesizable binaries or encrypted RTL for the MAC core

·         Source code RTL (Verilog) for I2C, MDIO, RMON and Register-File blocks  

·         Self checking behavioral models and test benches for simulation

·         Constraint files and synthesis scripts for design compilation

·         A complete PCIe/UART host interface based reference design with:

o        Top level wrapper (source files, Verilog) for user specific customizations

o        Source files (Verilog) for the PIC Express application layer

o        Binaries for the L2 packet generator and checker

o        PCIe driver/API (source files, C) for Linux

o        UART and command interpreter blocks with the optional UART host interface 

o        GUI application (Linux only for PCIe,  Linux and Windows for UART) for interfacing to the reference design

·         Design Guide(s) and user manuals

·         USA based technical support by developers

Price:

Supported Development Boards:

Xilinx Virtex-6	Altera Stratix IV GT	Xilinx Virtex-5	Xilinx Virtex-6 HXT	Xilinx Virtex-6 HXT
Xilinx Virtex-7	Altera Stratix V	Xilinx Kintex-7

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