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SDI
Audio Embedder IP Core
Overview:
The CWda42 implements an ancillary data packet embedder for SDI. It is
able to insert the contents of one audio group (4 channels). This
implementation is restricted to 20 audio bits per sample, hence the
extended data structure described in the ANSI/SMPTE 272M standard (data
extension to support 24 audio bits per sample) is not implemented in the
present version.
The CWda42 uses two clocks. All input signals are sampled on the rising
edge of the audio clock signal. The other clock, video clock, is used to
output the auxiliary data. The video and audio clocks must be derived
from the same source.
The audio samples inputs use the CW_LINK format. AES auxiliary
information is also inserted in the ancillary packets. This information
includes the Validity, Channel Status, and User bits.

Functional description:
Input FIFO: receives samples
from a CW-Link packet at the audio clock rate and outputs them at the
video clock rate.
UDW Generator:
receives the CW-Link samples from the Input FIFO and generates the
UDW words according to the ANSI/SMPTE 272M
standard.
Ancillary Data
Multiplexer: selects the appropriate input (did, dbn, dc or udw) in
order to output the anc_data stream.
Data Address Generator: Calculates and outputs the address
correspondent to the UDW currently on anc_data.
Control Unit:
Generates the control signals to all the other components in order to
build the ancillary data stream. This process is started by
the signal ready (if the input FIFO has data available to send), while
the signal pkt_sent flags the end of the sending of the current CW-Link
packet.
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Key Features:
- Supports the ANSI/SMPTE 272M standard
- Supports 20 bits of audio data
- Supports sample rates that bear a rational
relationship to the video clock (most common is 48 kHz)
- Extracts ancillary control bits from the incoming
cw_link signal
- Extracts all active channels in the selected audio
group (up to 4 audio channels)
Applications:
Serial Digital Interface video transmitters
Benefits:
Easy way to add audio to your SDI video
stream.
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Deliverables:
• Detailed datasheet and user documentation for system integration.
• HDL testbench covering all functionalities of the core and including
automatic
verification of the correctness of the responses.
• Options:
o FPGA netlist
o HDL (VHDL or VERILOG) source code.
o Simulation script..
o Prototyping boards.
Part Number:
CWda42
Price:

How To Purchase
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Implementation Results:
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Technology |
Gate Count |
RAM |
Frequency (audio_clk) |
Frequency (video-clk) |
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UMC 180 nm |
1 K |
128x26 bit |
1.00 GHz |
770 MHz |
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Family |
Example Device |
Fmax for video_clk
(MHz) |
Slices |
IOB |
GCLK |
BRAM
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Design
Tool |
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Spartan-3™ |
XC3S50-4 |
190.1 |
111 |
63 |
2 |
2 |
ISE 8.1 |
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Spartan-IIE™ |
XC2S50E-6 |
142.1 |
170 |
61 |
2 |
2 |
ISE 8.1 |
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Virtex-II Pro™ |
XC2VP2-5 |
256.7 |
105 |
63 |
2 |
2 |
ISE 8.1 |
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Virtex-II™ |
XC2V40-4 |
222.5 |
106 |
63 |
2 |
2 |
ISE 8.1 |
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Virtex-4™ |
XC4Vfx12-10 |
269.8 |
121 |
63 |
2 |
2 |
ISE 8.1 |
Other Digital Audio IP Cores:
|
IP Name/Part # |
Description |
| CWda03 |
SPDIF-AES/EBU to I2S Converter
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| CWda04 |
I2S to SPDIF-AES/EBU Converter
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| SPDIF-CWda14 |
Configurable SPDIF-AES/EBU Receiver |
| SPDIF-CWda15 |
Configurable SPDIF-AES/EBU Transmitter |
| I2S-CWda16 |
Configurable
Digital Audio Serial Input |
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I2S-CWda17 |
Configurable
Digital Audio Serial Output |
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SDI-CWda41 |
SDI Audio De-embedder |
| SDI-CWda42 |
SDI Audio Embedder |
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CWda30 |
3rd Order Stereo Digital Audio
Sigma-Delta Modulator
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SRC-CWda50 |
Stereo / Mono Sample Rate Converter |
| SRC-CWda52 |
Multi-Channel Audio Sample Rate Converter (ASRC) |
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