Within ISE design environment, ISE Simulator provides:

■ Mixed VHDL and Verilog simulation
■ Integrated wave editor for test bench creation
■ Behavioral/RTL simulation prior to synthesis
■ Timing simulation after place and route or fitting
■ Design hierarchy, waveform, and console views
■ Source-level debugging capabilities
■ Command-line console features TCL interface
■ "Generate Expected Results" process generates expected design output behavior based on input stimulus
■ The ability to generate Value Change Dump (VCD) or XAD files for use in power estimation (XPower)

► Key Features
■ Simulation support for all of Xilinx leading devices
■ VHDL-93 language support
■ Verilog-2001 language support
■ An intuitive user interface including:
- Waveform Editor window (used for graphical test bench creation)
- Waveform Display window
- Hierarchy Browser window
- Signals window
- Advanced Search capability to find signals in any scope of design
- Filter capability to view only what is pertinent to your needs
- Tcl-based Simulation Console window
■ Signal grouping
■ Support for incremental compilation
■ Complete printing support
■ Source code debugging for accelerating design troubleshooting and timing simulations

► System Requirements
- Microsoft Windows XP Professional (32-bit only)
- Microsoft Windows Vista Business (32-bit only)
- Red Hat Enterprise Linux 4 WS (32-bit and 64-bit)
- Red Hat Enterprise Linux 5 Desktop (32-bit and 64-bit)
- SUSE Linux Enterprise 10 (32-bit and 64-bit)

►Software Requirements
ISE Foundation Software